Many modern Complementary Metal Oxide Semiconductor (CMOS) processes have a large number of metal layers (e.g., 8-18 layers) for use later in process, i.e., the metal layers are higher and higher, e.g., farther away from the substrate.
FIG. 1A illustrates a cross-sectional view of a conventional CMOS device 10 constructed according to a conventional wafer process. In the example shown in FIG. 1A, the wafer process supports five metal layers, named “M1” through “M5” above the substrate 12. Within the substrate 12 a Field Effect Transistor (FET) may be built within a region of the substrate 12 referred to as the “device region” 14 using source/drain (S/D) diffusion layers 16. An M1 layer 18 may be connected to the S/D diffusion layer 16 via one or more S/D contacts 20. An M2 layer 22 may be connected to the M1 layer 18 through one more M2/M1 vias 24, which may be located over the S/D contact 20.
The S/D diffusion layer 16 is within a portion of the substrate 12 that is referred to herein as the “device region” 14, because semiconducting devices are constructed within this layer, e.g., one or more source diffusions are separated from one or more drain diffusions by a gate (not shown in the cross-section in FIG. 1A). Other layers—namely, the M2 layer 22, the M2/M1 via 24, the M1 layer 18, and the S/D contact 20—are hereinafter referred to as “FET connection layers 20,” or simply “FET layers 20,” because FETs are constructed using conductive structures within these layers. The higher layers shown in FIG. 1A—an M5 layer, an M5/M4 via, an M4 layer 28, an M4/M3 via, an M3 layer 26, and an M3/M2 via—are not used to create FETs but are instead used for chip-wide interconnects and can also be used to create capacitor structures. These layers are hereinafter referred to as “routing/capacitor layers,” “routing layers,” or simply “routing metal.”
In the example illustrated in FIG. 1A, a capacitor has been formed using routing/capacitor layers, i.e., from the M3 layer 26 (which forms the bottom plate of the capacitor) and the M4 layer 28 (which forms the top plate of the capacitor) separated by an oxide/passivation layer. Capacitors having this structure are referred to as Metal-Insulator-Metal (MIM) capacitors. The M5 layer, M5/M4 via, and M4/M3 via provide electrical contact to the capacitor plate structure created using the M3 layer 26 and the M4 layer 28. Thus, FIG. 1A illustrates the point that conventional CMOS processes use FET layers to create FETs and use routing layers for interconnects and to create capacitors.
However, while having a large number of metal layers simplifies routing by providing additional interconnect layers, this flexibility comes at a cost—namely, the expense of the additional material and process costs required to provide those layers.
As the CMOS device 10 moves for nanometer feature sizes, the lateral distance between the metal layers becomes small enough such that the lateral capacitance has significant capacitance density. As a result of this reduction in feature size, a different capacitor structure becomes possible. An example is shown in FIG. 1B.
FIG. 1B illustrates a cross-sectional view of another conventional CMOS device 30 constructed according to a conventional wafer process. In the example shown in FIG. 1B, a “stack” of metal is constructed of routing layers (i.e., the M5 layer, M5/M4 via, M4 layer 28, M4/M3 via, and M3 layer 26) to form vertical plates of a capacitor. Capacitors having this structure are referred to as Metal-Oxide-Metal (MOM) capacitors. In the example shown in FIG. 1B, there are six stacks, labeled S1 through S6. Odd-numbered stacks are connected to each other to form one plate of the capacitor, and even-numbered stacks are connected to each other form the other plate of the capacitor. However, many foundry process design kit-available MOM devices have poor performance due to design restrictions to accommodate process limitations. Moreover, not all processes have a large number of metal layers; in such cases, the traditional lateral MOM capacitance structure leads to poor performance.
FIGS. 2A and 2B illustrate two types of Radio Frequency (RF) switches. RF switches are commonly constructed of several FETs connected in series. FIG. 2A shows a Direct Current (DC)-coupled switch, in which the FETs are directly connected to each other, and FIG. 2B shows one stage of an AC-coupled switch, in which the FETs are connected to each other via capacitors, each labeled “CAP” in FIG. 2B. Both types of switches use bias networks to provide proper operating conditions to each FET in series, but DC-coupled switches, such as the one in FIG. 2A, typically require a charge pump or other voltage-shifting circuit to provide the proper DC bias required by each stage, while AC-coupled switches do not.
For example, to turn off the stage of the AC-coupled switch in FIG. 2B it is sufficient to provide 0 volts to the gate of the FET and to provide the supply voltage V volts to the source and drain of the FET. In contrast, each FET of the DC-coupled switch in FIG. 2A must be provided with a different bias voltage depending upon the position of the FET in the chain of FETs. As a result, AC-coupled switches require less bias circuitry, which reduces device complexity. Since charge pumps or similar circuits needed by DC-coupled switches typically occupy significant die space and require multiple, large capacitor structures, AC-coupled switches may be made with a smaller die area, which reduces wafer costs.
There are also disadvantages to AC-coupled switches, however, especially for RF switches that are used in receive, transmit, and transceiver signal paths. In the uplink carrier aggregation and ultra-high bandwidth and 5 Gigahertz (GHz) bands, the signal at the low-noise amplifier input can become moderately large. In such a case, it is necessary to stack multiple FETs, which distributes the input voltage across multiple FETs, thus avoiding subjecting any one FET to overvoltage conditions. In the receive case, the switch Insertion Loss (IL) goes directly into noise figure budget, thus there is a need to minimize switch IL. For example, a typical 45 nanometer silicon-on-insulator CMOS has a figure of merit of 84 femtoseconds (fs) and can get very low IL of about 0.05 Decibels (dB). MIM capacitors are expensive (extra masks), so metal capacitors become attractive. Thus, AC-coupled RF switches require many stages, with each stage having one or more metal capacitors.
The conventional structures illustrated in FIGS. 1A and 1B, and the wafer processes that are used to create them, suffer distinct disadvantages when used for AC-coupled switches and other circuits where FETs are connected in series via capacitors: the connections between one stage and the next involve creating conductive paths from the FET layers up to the routing metal layers and back down to the FET layers 20 for the next amplification stage. This up-and-down routing is repeated for each stage. Thus, AC-coupled switches constructed according to conventional processes, such as those illustrated in FIGS. 1A and 1B, require additional mask layers for not only the capacitor structures between stages but also for making the routing connections from the FET layer to the routing metal layers and back again as well as for other connections. As a result, high metal layer count processes are used to make AC-coupled switches, even when nanometer-scale, low metal layer processes are available.
Thus, there is a need for AC-coupled switch and metal capacitor structures for nanometer-scale or low metal layer count processes.